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| P R E L I M I N A RY I N F O R M AT I O N ICS557-07 2:1 MULTIPLEXER CHIP FOR PCI-E Description The ICS557-07 is a 2:1 HCSL multiplexer chip that allows the user to select one of the two input pairs of HCSL (Host Clock Signal Level) or LVDS inputs and fans out to one pair of differential HCSL outputs. This chip is suited especially for PCI-Express applications, where there is a need to select the PCI-Express clock locally from the PCI-E card or from the motherboard. Features * * * * * Packaged in 16-pin TSSOP Available in Pb (lead) free package Operating voltage of 3.3 V Low power consumption Input differential clock of up to 200 MHz (can accept LVDS, HCSL) differential pair) * Output, one pair (HCSL, 0.7 V Current mode * Jitter 60 ps (peak-to-peak) * Operating frequency of 80 MHz to 200 MHz Block Diagram VDD 3 OE IN1 IN1 IN2 IN2 CLK MUX 2 to 1 CLK 3 SEL GND PD Rr (IREF) MDS 557-07 B I n t e gra te d C i r c u i t S y s t e m s 1 525 Race Stre et, San Jo se, CA 9 5126 Revision 041405 te l (40 8) 2 97-12 01 w w w. i c st . c o m P R E L I M I N A R Y I N F O R M AT I O N ICS557-07 2:1 Multiplexer Chip for PCI-E Pin Assignment VDD IN1 IN1 PD IN2 IN2 OE GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL GND GND VDD VDD CLK CLK IREF Select Table SEL 0 1 Input Pair selected IN2/ IN2 IN1/ IN1 16-pin (173 mil) TSSOP Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name VDD IN1 IN1 PD IN2 IN2 OE GND Rr(IREF) CLK CLK VDD VDD GND GND SEL Pin Type Power Input Input Input Input Input Input Power Output Output Output Power Power Power Power Input HCSL/LVDS true input signal 1. Pin Description Connect to +3.3 V. Supply voltage for Input clocks. HCSL/LVDS complimentary input signal 1. Powers down the chip and tri-states outputs when low. Internal pull-up resistor. HCSL/LVDS true input signal 2. HCSL/LVDS complimentary input signal 2. Provides fast output on, tri-states output (High = enable outputs; Low = disable). Internal pull-up resistor. Connect to ground. Precision resistor attached to this pin is connected to the internal current reference. HCSL differential complimentary clock . HCSL True clock. Connect to +3.3 V. Supply Voltage for output clocks. Connect to +3.3 V. Supply Voltage for output clocks. Connect to ground. Connect to ground. SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor. MDS 557-07 B In te grated Circuit Systems 2 525 Ra ce Street, San Jose, CA 9512 6 Revision 041405 tel (4 08) 297-1 201 w w w. i c s t . c o m P R E L I M I N A R Y I N F O R M AT I O N ICS557-07 2:1 Multiplexer Chip for PCI-E Applications Information External Components A minimum number of external components are required for proper operation. Output Structures IREF =2.3 mA 6*IREF Decoupling Capacitors Decoupling capacitors of 0.01 F should be connected between VDD and the ground plane (pin 4) as close to the VDD pin as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into ICS pin. Crystal A 25 MHz fundamental mode parallel resonant crystal with CL = 16 pF should be used. This crystal must have less than 300 ppm of error across temperature in order for the ICS557-07 to meet PCI Express specifications. R R 475 See Output Termination Sections - Pages 3 ~ 5 Crystal Capacitors Crystal capacitors are connected from pins X1 to ground and X2 to ground to optimize the accuracy of the output frequency. CL= Crystal's load capacitance in pF Crystal Capacitors (pF) = (CL- 8) * 2 For example, for a crystal with a 16 pF load cap, each external crystal cap would be 16 pF. (16-8)*2=16. General PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-07.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Current Source (Iref) Reference Resistor - RR If board target trace impedance (Z) is 50, then RR = 475 (1%), providing IREF of 2.32 mA. The output current (IOH) is equal to 6*IREF. Output Termination The PCI-Express differential clock outputs of the ICS557-07 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The ICS557-07can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section MDS 557-07 B In te grated Circuit Systems 3 525 Ra ce Street, San Jose, CA 9512 6 Revision 041405 tel (4 08) 297-1 201 w w w. i c s t . c o m P R E L I M I N A R Y I N F O R M AT I O N ICS557-07 2:1 Multiplexer Chip for PCI-E Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS557-07. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Protection (Input) 5.5 V Rating -0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 125C 260C 2000 V min. (HBM) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70C Parameter Supply Voltage Input High Voltage 1 Symbol V VIH VIL IIL IDD IDDOE IDDPD Conditions OE, SEL, PD OE, SEL, PD 0 < Vin < VDD 50, 2 pF OE =Low No load, PD =Low Input pin capacitance Output pin capacitance CLK, each output Min. 3.135 2.0 VDD-0.3 -5 Typ. Max. 3.465 VDD +0.3 0.8 5 40 20 400 7 6 5 Units V V A mA mA A pF pF nH k k Input Low Voltage1 Input Leakage Current2 Operating Supply Current Input Capacitance Output Capacitance Pin Inductance Output Resistance Pull-up Resistor CIN COUT LPIN ROUT RPU 3.0 110 1 Single edge is monotonic when transitioning through 2 Inputs with pull-ups/-downs are not included. region. MDS 557-07 B In te grated Circuit Systems 4 525 Ra ce Street, San Jose, CA 9512 6 Revision 041405 tel (4 08) 297-1 201 w w w. i c s t . c o m P R E L I M I N A R Y I N F O R M AT I O N ICS557-07 2:1 Multiplexer Chip for PCI-E AC Electrical Characteristics - CLKOUTA/CLKOUTB Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature 0 to +70C Parameter Input Frequency Output Frequency Input High Voltage Input Low Voltage Differential Input Voltages Input Offset Voltage Output High Voltage Output Low Voltage Crossing Point Voltage1,2 Crossing Point Voltage1,2,4 Jitter, Cycle-to-Cycle1,3 Rise Time 1,2 1,2 1,2 1,2 Symbol Conditions Min. 80 80 Typ. Max. 200 200 Units MHz MHz mV mV mV V mV mV mV mV ps VIH VIL (VID) (VIS) VOH VOL HCSL HCSL LVDS LVDS HCSL HCSL Absolute Variation over all edges 660 -150 250 1.125 660 -150 250 700 0 350 1.25 700 0 350 850 450 1.375 850 550 140 1,2 60 tOR tOF From 0.175 V to 0.525 V From 0.525 V to 0.175 V 175 175 332 344 700 700 125 45 55 10 10 3.0 4 ps ps ps % s s ms ns Fall Time1,2 Rise/Fall Time Variation1,2 Duty Cycle1,3 Output Enable Time Stabilization Time Input to Output Delay 1 2 3 4 5 5 All outputs All outputs tSTABLE From power-up VDD=3.3 V Measured at crossing points Output Disable Time5 Test setup is RL=50 ohms with 2 pF, Rr = 475 (1%). Measurement taken from a single-ended waveform. Measurement taken from a differential waveform. Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. CLK and CLK pins are tri-stated when OE is Low. CLK and CLK are driven differential when OE is High unless its PD = low. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol JA JA JA JC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. 93 78 65 20 Max. Units C/W C/W C/W C/W Thermal Resistance Junction to Case MDS 557-07 B In te grated Circuit Systems 5 525 Ra ce Street, San Jose, CA 9512 6 Revision 041405 tel (4 08) 297-1 201 w w w. i c s t . c o m P R E L I M I N A R Y I N F O R M AT I O N ICS557-07 2:1 Multiplexer Chip for PCI-E HCSL Output Loads IREF =2.3 mA 6*IREF RL 475 RL 50.2 RL 50.2 700 mV 0 tOR 0.52 V 0.175 V 500 ps 500 ps tOF 0.52 V 0.175 V MDS 557-07 B In te grated Circuit Systems 6 525 Ra ce Street, San Jose, CA 9512 6 Revision 041405 tel (4 08) 297-1 201 w w w. i c s t . c o m P R E L I M I N A R Y I N F O R M AT I O N ICS557-07 2:1 Multiplexer Chip for PCI-E Marking Diagram 16 9 Marking Diagram (Pb free) 16 9 557G-07 ###### YYWW$$ 1 8 1 557G07LF ###### YYWW 8 Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. "LF" denotes Pb free package. 4. Bottom marking: (origin). Origin = country of origin if not USA. MDS 557-07 B In te grated Circuit Systems 7 525 Ra ce Street, San Jose, CA 9512 6 Revision 041405 tel (4 08) 297-1 201 w w w. i c s t . c o m P R E L I M I N A R Y I N F O R M AT I O N ICS557-07 2:1 Multiplexer Chip for PCI-E Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters Symbol Min Max Inches Min Max Index Area A -0.05 0.19 0.09 4.90 4.30 1.20 0.15 0.30 0.20 5.10 4.50 -0.002 0.007 0.0035 0.193 0.169 0.047 0.006 0.012 0.008 0.201 0.177 E H a b c D E e Pin 1 0.65 Basic 6.40 Basic 0.45 0.75 0.0256 Basic 0.252 Basic 0.018 0.030 D H L a e b c L A Ordering Information Part / Order Number ICS557G-07 ICS557G-07T ICS557G-07LF ICS557G-07LFT See Page 4 Marking Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP Temperature 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 557-07 B In te grated Circuit Systems 8 525 Ra ce Street, San Jose, CA 9512 6 Revision 041405 tel (4 08) 297-1 201 w w w. i c s t . c o m |
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